For integrated circuits, the role of the input/output (I/O) pad likely acts as a bridge which communicates the chip itself to another. An ideal I/O pad serves as a buffer without signal gain or degradation, as is shown in FIG. 1a with an input terminal A and an output terminal Z. As a signal pulse imposes on the input terminal A, the signal is fed into the buffer, usually an even numbers of inverters, for a time delay of about several nano-seconds, the output terminal Z should get the same pulse width as the original one.
If a low pass filter is added to the I/O pad to make the I/O pad have the function of filtering, it may result in malfunctioning. An example is shown in FIG. 1b. It shows a low pass filter I/O pad series connected with two inverters having a capacitor C in between, where “A” is an input terminal, “Z” being an output terminal, and VCP is the terminals voltage of the capacitor C. Assuming the forgoing low pass filter circuit is desired to filter those pulses having short pulse width, such as 20 ns and below, the filter may get a malfunction due to the situation described below. Supposing a first pulse H1 having pulse width 15 ns is passed through the first inverter INV1, the signal charging the capacitor C to a voltage of VCP is followed. Since the VCP does not reach the threshold voltage VTH of the second inverter INV2, VZ=0 is resulted. Hence, the pulse H1 had been filtered out successfully. Thereafter, VA returns to its original level (e.g. 0) for a time duration L (e.g. 5 ns), and then the charges in the capacitor C, discharge through the first inverter INV1. However, if the capacitor C is not discharged completely within the time duration L, and a second pulse H2 following H1 is exerted on terminal A, the VCP may still possibly attain to the threshold voltage of VTH of the second inverter INV2 even though the pulse width of the second pulse H2 is smaller than 20 ns due to the residue charges in the capacitor C. In other words, the interval between pulses H1 and H2 becomes critical. Thus, taking the time duration L=5 ns as an example, as shown in FIG. 1b, the pulse H2 may make the VCP exceed VTH while approaching the ending of the pulse H (it may be about 10 ns). As a result, an undesired pulse H2 appears at the output terminal Z.
An object of the present invention is thus to provide a circuit, which utilizes feed back signals associated with MOS (Metal-Oxide-Semiconductor) transistors, to reset the charging/discharging circuit. The high current drivability of the MOS makes the operation of fast charging/discharging possible, and prevents the malfunction due to residual charges.